1. Field of the Invention
The present invention relates to a semiconductor substrate device in which a parasitic capacitance generated between the semiconductor substrate and circuit elements such as metal wiring, passive elements, active elements, and the like is reduced; and a method for fabricating the semiconductor substrate device.
2. Description of the Related Art
In recent years, the market of mobile multimedia devices using radio communication, including portable information devices, such as digital cordless phones, e.g., digital mobile phones and PHS (personal handy-phone system) devices, has been expanded. In the research institutes of manufacturers of mobile multimedia devices, colleges, and the like, techniques for improving high-frequency characteristics of a high-frequency device (e.g., a thin-film transistor) used in the mobile multimedia devices are being actively studied. One of the ways to improve the high-frequency characteristics is to reduce a parasitic capacitance generated between a semiconductor substrate, such as a silicon substrate, and circuit elements including wiring, such as metal wiring, and including elements, such as passive elements and active elements.
Methods for fabricating a semiconductor device in which the parasitic capacitance is reduced so as to improve the high-frequency characteristics are disclosed in, for example, Japanese Laid-Open Publication No. 03-196644 (hereinafter, referred to as xe2x80x9cdocument 1xe2x80x9d) and IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 45, No. 5, May 1998, pp. 1039-1045 (hereinafter, referred to as xe2x80x9cdocument 2xe2x80x9d).
First, a method of document 1 will be described with reference to FIGS. 4A to 4D.
FIGS. 4A to 4D are cross-sectional views, each illustrating a step of a fabrication method of a semiconductor integrated circuit in which parasitic capacitance is reduced.
(1) As shown in FIG. 4A, on a top surface of a semiconductor substrate 1 which includes a circuit element (not shown), a bonding pad 2 is provided in a predetermined position. The semiconductor substrate 1 is polished from a bottom surface to have a thickness of about 150 xcexcm.
(2) As shown in FIG. 4B, photoresist layers 7 and 8 each having a thickness of 2 to 5 xcexcm are respectively formed on the entire top and bottom surfaces of the semiconductor substrate 1 covering the bonding pad 2. Then, an opening 8a is formed in the photoresist layer 8 on the bottom surface of the semiconductor substrate 1 in a position opposing the bonding pad 2.
(3) As shown in FIG. 4C, a cavity 3 is formed in a bottom portion of the semiconductor substrate 1 by isotropic wet etching using the photoresist layers 7 and 8 as masks. An etchant including sulfuric acid, hydrogen peroxide, and water at a ratio of 1 to 4:1:1 is used.
(4) As shown in FIG. 4D, the photoresist layers 7 and 8 are removed. Thereafter, a silicon nitride film 6 is deposited on an inner surface of the cavity 3. Then, the resultant laminate is mounted on a metallized layer 5 of a ceramic package 4.
In the semiconductor integrated circuit fabricated by steps (1) to (4), the cavity 3 is formed in the bottom portion of the semiconductor substrate 1 in a position opposing the bonding pad 2. By providing the cavity 3 at this position, the parasitic capacitance generated between the semiconductor substrate 1 and the bonding pad 2 can be reduced.
Next, a method of document 2 will be described. Document 2 describes a method for fabricating a semiconductor device (e.g., a Silicon on Insulator (SOI) substrate device) in which parasitic capacitance generated between a substrate and a circuit element Is reduced. An inductor of the semiconductor device, which is a passive element, is used in a high-frequency device along with the semiconductor device. The parasitic capacitance generated between the substrate and the inductor is reduced, and thus a quality factor of the inductor is improved. Therefore, high-frequency characteristics of the high-frequency device are improved.
FIGS. 5A to 5E are cross-sectional views, each illustrating a step of a fabrication method of the semiconductor device.
(1) As shown in FIG. 5A, an insulating layer 11 having a thickness of 70 nm is laminated on an SOI substrate 10 having a thickness of 300 nm. Then, two gate oxide films 13 and an element isolation film 12 are formed on the insulating layer 11 by a LOCOS (Local Oxidation of Silicon) method. The two gate oxide films 13 straddle the element isolation film 12. A gate electrode 14 is formed on each of the gate oxide films 13.
(2) As shown in FIG. 5B, tungsten (W) films 15 are grown on each of the gate electrodes 14, and on source and a drain regions formed on either side of each of the gate electrodes 14 by a selective CVD (Chemical Vapor Deposition) method. Thus, aplurality of elements 19 are formed.
(3) As shown in FIG. 5C, on the tungsten films 15 above the source and drain regions, three-layer metal wiring is formed. Aluminum (Al) wiring 16, forming an inductor, is formed on a top surface of the three-layer metal wiring. Then, a passivation process is performed. Thus, a circuit element is formed.
(4) As shown in FIG. 5D, an opening 17 is provided by anisotropic etching. The opening 17 penetrates the laminate from the top surface of the three metal wiring to a top surface of the SOI substrate 10.
(5) As shown in FIG. 5E, a cavity 18 having a depth of about 100 nm from the top surface of the SOI substrate 10 is formed. The cavity 18 is formed by isotropic etching in which sulfur fluoride (SF6) is injected through the opening 17. The cavity 18 extends under one of the elements 19 which is closest to the opening 17.
As a result of performing steps (1) to (5), semiconductor device is provided in which the parasitic capacitance generated between the SOI substrate 10 and the inductor 16 is reduced by providing the capacity 18. The semiconductor device having such a structure allows the inductor 16 to have improved high-frequency characteristics.
In the methods described in each of the documents 1 and 2, the parasitic capacitance generated between the substrate and the circuit elements can be reduced by forming a cavity having a low dielectric constant in the semiconductor substrate in a portion below the circuit elements (wiring, elements, and the like).
However, these methods have the following problems.
(1) It is required to form a cavity in a semiconductor substrate after the circuit elements and the like are formed on the semiconductor substrate to fabricate an LSI or the like. Accordingly, the number of steps of the fabrication method increases and the circuit elements formed on the substrate may be damaged when forming the cavity.
(2) Especially, in the method of document 2, it is required to reserve a region for forming an opening which penetrates a semiconductor substrate of a semiconductor device from a top surface having the circuit elements thereon. Thus, when the arrangement of multi-layer wiring becomes complicated and circuit elements are positioned close to each other, accurately forming an opening becomes difficult.
According to one aspect of the invention, there is provided a semiconductor substrate device, comprising: a first semiconductor substrate including a concave-convex surface; and a second semiconductor substrate having an insulating film on a surface thereof. The first semiconductor substrate and the second semiconductor substrate are brought together so that the surface of the first semiconductor substrate and the insulating film provided on the surface of the second semiconductor substrate contact each other to form a cavity in the semiconductor substrate device.
In one embodiment of the invention, the concave-convex surface of the first semiconductor substrate is defined by a plurality of convex portions formed at equal intervals.
According to another aspect of the invention, there is provided a method for fabricating a semiconductor substrate device, comprising the steps of: providing a resist layer having a predetermined pattern on a first insulating film on a first semiconductor substrate; performing isotropic or anisotropic etching of the first insulating film by using the resist layer as a mask, and performing anisotropic etching of the first semiconductor substrate by using the resist layer as a mask to form a concave-convex portion in a surface of the first semiconductor substrate to provide the first semiconductor substrate with the concave-convex surface; and removing the resist layer and the first insulating film, and then bringing the first semiconductor substrate and a second semiconductor substrate together so that the surface of the first semiconductor substrate and a second insulating film provided on a surface of the second semiconductor substrate contact each other.
In one embodiment of the invention, the method further comprises the step of thinning the second semiconductor substrate from a surface opposite to the surface thereof provided with the second insulating film after the step of bringing the first semiconductor substrate and the second semiconductor substrate together.
In one embodiment of the invention, the anisotropic etching of the first semiconductor substrate is performed by using KOH.
Thus, the invention described herein makes possible the advantages of providing a semiconductor substrate device which ensures the reduction of parasitic capacitance when elements are provided thereon, and a method for fabricating the semiconductor substrate device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.